1. Field of the Invention
The present invention relates to a semiconductor device, for example, a semiconductor device including a storing mechanism for allowing write-in or read-out operations as one access unit of a piece of composite data containing a piece of main data and additional information data and an accessing mechanism for performing the write-in or read-out operation. More particularly, the present invention relates to systems, methods and computer program product that include the storing mechanism and the accessing mechanism on one semiconductor chip. The present invention also relates to an image data processing apparatus for processing a piece of composite data containing pieces of an image data and additional information data associated with the image data.
2. Discussion of the Background
According to related art semiconductor devices containing data storing mechanisms that handle a piece of composite data containing a piece of main data and additional information data associated with the main data, the main data and the additional information data have been, in general, separately stored and separately written in or read out. In particular, in related art image data processing apparatuses, image data and additional information data associated with the image data have been, in general, separately stored in respective memories and separately handled, wherein the image data and the additional information data have been separately read out from the memories and separately processed.
On the other hand, in a memory block for storing image data and additional information data associated therewith, image data has been written or read in or from the memory block on the basis of an address designated from an externally originated request. Accordingly, in the case of writing or reading a plurality of pieces of image data in or from the memory block by one access, addresses have been designated one-by-one sequentially from a specific starting position, and pieces of image data have been sequentially read or written in or from memory locations designated by the addresses.
In the case of handling pieces of image data having a hierarchy structure, for example, pieces of image data identical in content but different in resolution, pieces of pixel data having different resolutions have been separately stored in respective memories. Accordingly, in the case of handling image data having different resolutions, pieces of image data have been separately read or written from or in the memories on the basis of respective designated addresses.
In the above-described related art image data processing apparatus, access to image data is generally performed on the basis of an address designated from an external requesting source. Accordingly, for example, in a processing operation such as motion estimation, if it is intended to realize high-speed, high-efficient motion detection by reducing the offset and area of a search region on the basis of a motion vector detected by image data in the previous frame, there occur inconveniences such as complicated address control at the time of memory access, and that a multiplicity of circuit portions for address control must be provided and thereby the scale of the processing circuit must be increased.
In the case of forming pieces of image data in hierarchies having different resolutions, it is required that pieces of image data are stored for each hierarchy having the corresponding resolution, and when performing data processing, pieces of image data are written or read out by access to separate memories storing pieces of image data having different resolutions. Accordingly, there occurs an inconvenience that access to image data becomes complicated and the volumes of memory for storing data becomes large, with an increase in the number of the hierarchies.
In the case of acquiring all pieces of pixel data in a specific object stored in image memories, it is required to sequentially designate addresses of the memories, in which all the pieces of pixel data in the object remain as stored, from external to the memories and to sequentially read all the pieces of pixel data from the designated memories. In this case, there occurs an inconvenience related to complicated address control, to reduce the degree of freedom in address control at the time of reading the image data.